An electronic computer aided design (“E-CAD”) package uses an activity factor within a power analysis tool to determine switching power requirements associated with a signal of a Very Large Scale Integration (“VLSI”) circuit design. The activity factor defines the number of transitions the signal makes during one half of a clock cycle; the clock reference signal therefore has an activity factor of one. By determining activity factors for all signals in a VLSI circuit design, the power analysis tool may calculate switching power requirements for the entire VLSI circuit design. The switching power consumed by a particular signal is dependent on the frequency of transitions made by the signal and the capacitance of the signal net carrying the signal. The higher the signal frequency, the more often the net capacitance charges and discharges, increasing the switching power requirements.
The power analysis tool uses a vector logic simulator to simulate and determine the activity factor associated with each signal net of the VLSI circuit design. This simulation may take several hours or days since the VLSI circuit design typically has billions of engineering components. The delay associated with the simulation reduces productivity; continuous lost productivity due to lengthy engineering development slows technology advancement and can result in significant costs, as well as lost business.
To reduce the time period associated with determining switching power requirements of the VLSI circuit design, an average activity factor is often estimated and applied to all signal nets of the VLSI circuit design, thereby removing the need to separately calculate activity factors for each signal net. This estimate reduces the number of calculations required in determining switching power requirements of the VLSI circuit design, but it also reduces the accuracy of the results.